/*
* srams.h -- Biblioteca de memorias RAM estáticas.
* Ultima modificación: 8-11-00.
* gse.
*/
/*
* Celda básica de memoria, basada en un cerrojo SR asíncrono.
* Digital Logic and Computer Design. M. Morris Mano, pag 295.
*
* Responde a la tabla de verdad:
*
* select write | Qn+1 out
* -------------+---------
* 0 0 | Qn Z
* 0 1 | Qn Z
* 1 0 | Qn Qn
* 1 1 | in in
*
* y su implementación física es:
*
* write
* +---+ | +----+
* |N |nin| +-+A | +------+
* +-+O n+---|-|-+N a0+---+R Qn+- qn
* | |T | +-|-+D | r | FFSR |
* in --+ +---+ | | +----+ | Nor |
* | | | +----+ | |
* | | +-+A | | f | q +--------+
* +---------|-|-+N a1+---+S Q+----+BUFFER z+- out
* +-|-+D | s +------+ +----+---+
* | +----+ |
* +-------------+-------------+
* |
* select
*
* que en lo sucesivo será:
*
* write
* |
* +-----+-----+
* | |
* | |
* in --+ SRAM_BIT +-- out
* | |
* | |
* +-----+-----+
* |
* select
*
*/
class SRAM_BIT {
NOT n;
WIRE nin,r,s,q,qn;
AND a0,a1;
SR_LATCH_NOR f;
BUFFER_Z b;
public:
void run(WIRE &in, WIRE &select, WIRE &write, WIRE &out);
};
/*
* Este es el diseño de un bloque de 4x4 bits de memoria SRAM.
* Se utilizará más adelante en la construcción de la memoria
* SRAM mediante replicación.
*
* blksel | |in[3] |in[2] |in[1] |in[0]
* | | | | | write
* <-------|----|----+------|----+------|----+------|----+------+--
* | | | | | | | | | |
* | | +-v-+ | +-v-+ | +-v-+ | +-v-+ |
* | +--> b +--+ +--> b +--+ +--> b +--+ +--> b +--+ |
* | | +-+-+ | | +-+-+ | | +-+-+ | | +-+-+ | |
* +-A | |s[0]| | | | | | | | | | |
* +-|-N--|----+----|-|----+----|-|----+----|-|----+ | |
* sel[0]| | D | | | | | | | | |
* ------+-|----|---------|-|---------|-|---------|-|---------|-|--->
* | | +----|-|----+----|-|----+----|-|----+----|-+
* | | | | | | | | | | | | | |
* | | +-v-+ | | +-v-+ | | +-v-+ | | +-v-+ | |
* | +--> b +--+ +--> b +--+ +--> b +--+ +--> b +--+ |
* | | +-+-+ | | +-+-+ | | +-+-+ | | +-+-+ | |
* +-A | |s[1]| | | | | | | | | | |
* +-|-N--|----+----|-|----+----|-|----+----|-|----+ | |
* sel[1]| | D | | | | | | | | |
* ------+-|----|---------|-|---------|-|---------|-|---------|-|--->
* | | +----|-|----+----|-|----+----|-|----+----|-+
* | | | | | | | | | | | | | |
* | | +-v-+ | | +-v-+ | | +-v-+ | | +-v-+ | |
* | +--> b +--+ +--> b +--+ +--> b +--+ +--> b +--+ |
* | | +-+-+ | | +-+-+ | | +-+-+ | | +-+-+ | |
* +-A | |s[2]| | | | | | | | | | |
* +-|-N--|----+----|-|----+----|-|----+----|-|----+ | |
* sel[2]| | D | | | | | | | | |
* ------+-|----|---------|-|---------|-|---------|-|---------|-|--->
* | | +----|-|----+----|-|----+----|-|----+----|-+
* | | | | | | | | | | | | |
* | | +-v-+ | | +-v-+ | | +-v-+ | | +-v-+ |
* | +--> b +--+ +--> b +--+ +--> b +--+ +--> b +--+
* | +-+-+ | +-+-+ | +-+-+ | +-+-+ |
* +-A |s[3]| | | | | | |
* +---N-------+----|------+----|------+----|------+ |
* sel[3]| D | | | |
* ------+----------------|-----------|-----------|-----------|----->
* v v v v
* out[3]| out[2]| out[1]| out[0]|
*
* En adelante, a este dispositivo lo referenciaremos como:
*
* selblk in[3-0]
* | | | | |
* +-+--+-+-+-+-+
* | +-- write
* sel[0] --+ |-- sel[0] (son las mismas entradas)
* sel[1] --+ 4x4 |-- sel[1]
* sel[2] --+ SRAM |-- sel[2]
* sel[3] --+ |-- sel[3]
* +----+-+-+-+-+
* | | | |
* out[3-0]
*
*/
class BIT_4x4_Array {
SRAM_BIT b[4][4];
AND a[4];
WIRE s[4];
public:
void run(WIRE in[4], WIRE &blksel, WIRE sel[4], WIRE &write, WIRE out[4]);
};
/*
* Memoria SRAM de 16x4 bits, usando 4 bloques de 4x4 bits.
*
* select------>/| blksel[] in[3]
* |0+----------------------------------------------+ |in[2]
* __|1+--------------------------------+ | | |in[1]
* | |2+------------------+ | | | | |in[0]
* addr[3-2]| |3+----+ | | | | | | |
* | \| | +-----------|-+-----------|-+-----------|-+ | | |
* | | | +---------|-|-+---------|-|-+---------|-|-+ | |
* | | | | +-------|-|-|-+-------|-|-|-+-------|-|-|-+ |
* | | | | | +-----|-|-|-|-+-----|-|-|-|-+-----|-|-|-|-+ w
* addr[3-0]| | | | | | | | | | | | | | | | | | | | | r
* ---------+ /|sel +-+-+-+-++<--++-+-+-+-++<--++-+-+-+-++<--++-+-+-+-++<-i
* | |0+---> |---> |---> |---> | t
* addr[1-0]|__|1+---> 4x4 |---> 4x4 |---> 4x4 |---> 4x4 | e
* |2+---> SRAM |---> SRAM |---> SRAM |---> SRAM |
* |3+---> |---> |---> |---> |
* \| +--+-+-+-++ +--+-+-+-++ +--+-+-+-++ +--+-+-+-++
* | | | | | | | | | | | | | | | |
* +-|-|-|-------+-|-|-|-------+-|-|-|-------+ | | |
* +-|-|---------+-|-|---------+-|-|-------|-+ | |
* +-|-----------+-|-----------+-|-------|-|-+ |
* +-------------+-------------+-------|-|-|-+
* | | | |
* | | |out[0]
* | |out[1]
* |out[2]
* out[3]
* En adelante, el bloque será:
*
* in[3-0]
* |
* +-------+-------+
* | |
* select --+ |
* | 16x4 +-- write
* | SRAM |
* addr[3-0] --+ |
* | |
* +-------+-------+
* |
* out[3-0]
*/
class SRAM_16x4 {
BIT_4x4_Array blk[4];
DECOD_2_4 dec;
DECOD_2_4_SEL dec_sel;
WIRE sel[4],blksel[4];
public:
void run(WIRE &select, WIRE &write, WIRE addr[4], WIRE in[4], WIRE out[4]);
};
/*
* Memoria SRAM de 16x32 bits.
*
* Se trata de 32/4=8 bloques de 16x4 bits, direccionados en paralelo, pero que
* toman un dan bits de entrada y salida distintos.
*
* in[31-28] in[27-24] ... in[3-0]
* | | |
* +---+---+ +---+---+ +-...-+ +---+---+
* select --+ |-+ |-+ |-+ |
* | 16x4 +-| 16x4 +-| +-| 16x4 +-- write
* addr[3-0] --+ |-+ |-+ |-+ |
* +-------+ +-------+ +-...-+ +-------+
* | | |
* out[31-28] out[27-24] ... out[3-0]
*
* Dispositivo que en adelante será:
*
* in[31-0]
* |
* +-------+-------+
* | |
* select --+ |
* | 16x32 +-- write
* | SRAM |
* addr[3-0] --+ |
* | |
* +-------+-------+
* |
* out[31-0]
*/
class SRAM_16x32 {
SRAM_16x4 blk[8];
public:
void run(WIRE &select, WIRE &write, WIRE addr[4], WIRE in[32], WIRE out[32]);
};
/*
* Memoria SRAM de 64x32 bits
*
* addr[5,4] --------+ in[31-0]
* | |
* +--+--+ |
* select -------/0 1 2 3\ +-------+
* +-+-+-+-+-+ | |
* | | | | | +----+----------+
* | | | | | | |
* | | | +-----|--+ select |
* | | | | | blk[3] +-----+------- write
* addr[3-0] ---+-|-|-|-------|--+ 16x32 | |
* | | | | | | SRAM | |
* | | | | | | | |
* | | | | | +----------+----+ |
* | | | | | | |
* | | | | +-------+ +-------+ |
* | | | | | | | |
* | | | | | +----+----------+ | |
* | | | | | | | | |
* | | | +-------|--+ select | | |
* | | | | | blk[2] +--|--+
* +-|-|---------|--+ 16x32 | | |
* | | | | | SRAM | | |
* | | | | | | | |
* | | | | +----------+----+ | |
* | | | | | | |
* | | | +-------+ +-------+ |
* | | | | | | |
* | | | | +----+----------+ | |
* | | | | | | | |
* | | +---------|--+ select | | |
* | | | | blk[1] +--|--+
* +-|-----------|--+ 16x32 | | |
* | | | | SRAM | | |
* | | | | | | |
* | | | +----------+----+ | |
* | | | | | |
* | | +-------+ +-------+ |
* | | | | |
* | | +----+----------+ | |
* | | | | | |
* | +--------------+ select | | |
* | | blk[0] +--|--+
* +----------------+ 16x32 | |
* | SRAM | |
* | | |
* +----------+----+ |
* | |
* +-------+
* |
* out[31,0]
*
*/
class SRAM_64x32 {
SRAM_16x32 blk[4];
DECOD_2_4_SEL dec;
WIRE select[4];
public:
void run(WIRE &select, WIRE &write, WIRE addr[6], WIRE in[32], WIRE out[32]);
};